The present invention relates to devices, systems and methods for testing electronic circuits using automated test equipment, and more particularly to devices, systems and methods for testing systems-on-a-chip (SOC) or other integrated circuits. Manufacturers typically test SOC integrated circuits (ICs) in order to ensure proper functionality and reliability. One system commonly employed to test SOC ICs is the Agilent 93000 SOC Tester, which supports concurrent tests. Portions of the Agilent 93000 SOC tester are described in U.S. Pat. No. 6,756,778 to Hirschmann, entitled “Measuring and Calibrating a Test Head”; U.S. Pat. No. 5,558,541 to Botka et al., entitled “Blind Mate Connector for an Electronic Circuit Tester”; and U.S. Pat. No. 5,552,701 to Veteran et al, entitled “Docking System for an Electronic Circuit Tester”.
FIG. 1 shows the Agilent 93000 Tester 100, comprising a test head 110 with a device under test (DUT) interface 120; a manipulator 130 for positioning test head 110; a DUT board 150 that plugs into underlying DUT interface 120; a support rack 140 for supplying test head 110 with electrical power, water cooling and compressed air (not shown) and a computer workstation (not shown) that serves as the user interface to Tester 100. Test head 110 comprises tester electronics and additional analog modules. With current technology, test head 110 may be configured with 512 pins or 1024 pins, but this will likely increase in the future. The 512 pin test head supports 4 card cages while the 1024 pin test head supports 8 card cages. Each card cage may contain 8 digital boards or 8 analog modules, respectively. A single board has 16 pins, making 128 pins per cage. Thus, a 4-cage test head contain 512 pins and an 8-cage test head 1024 pins. During testing, a DUT is mounted on a contactor (not shown) on the DUT board 150, which is connected to the I/O channels by DUT interface 120. DUT interface 120 may comprise high performance coax cabling and spring contact pins or pogo pins, which establish electrical connection with DUT board 120.
DUT interface 120 provides docking capabilities to handlers and wafer probers. The docking mechanism is controlled by compressed air (not shown), and if required may also be operated manually. Test head 110 is usually a water-cooled system and receives its cooling water supply from support rack 140, which in turn is connected by two flexible hoses to the cooling unit (not shown). Manipulator 130 supports and positions test head 110 and provides 6 degrees of freedom for precise and repeatable connections between test head 100 and handlers or wafer probers.
Support rack 140 is attached to manipulator 130 and serves as the interface between test head 110 and an AC power source, cooling water source and compressed air source. Tester 100 may also comprise additional support racks such as analog support racks for installing additional analog instruments.
An HP-UX workstation (not shown) may serve as the interface between the user and tester 100. At the present time, Agilent 93000 SOC Series SmarTest software runs on the HP-UX workstation under the HP-UX operating system, although other suitable operating systems such as Linux or other workstations may certainly be used. SmarTest allows setups and test data to be downloaded to the test system, and further permits editing of such information. All testing is carried out in the test system. Results are read back by the workstation and displayed on the monitor. During test program execution, upload and download are typically not required since the test processors act independently from the workstation once the test program has begun running.
On the workstation, a diagnostic program can be run to check the system periodically or to identify the source of a problem. Configuration of Tester 100 involves assigning digital channel boards, power supplies, and analog instruments to specific channels of the test head and providing for associated mainframe components (such as an alternate master clock (AMC)) external to the test head. Test heat electronic components supply power to the various DUTs and perform measurements. Some test head functions and key elements are: 1) conversion and distribution of supply voltages; 2) interfacing via fiber optic cable to the workstation; 3) internal communication via data bus, address bus and control bus; 4) communication clock generation and distribution; 5) master clock generation and distribution; 6) high precision parametric measurement unit (HP PMU); 7) interfacing with external clock; 8) supplying power to the DUT; and 9) making channel measurements; among other things.
Each pin in the platform provides period, timing, levels, patterns and sequencing, enabling each tester pin to independently operate in any number of different modes. Instead of sharing testing resources, every pin supports a full range of tester modes, including clock, SCAN, BIST control, functional, APG and digital source and capture. Such flexibility in Tester 100 allows for on-the-fly grouping of pins into virtual ports to test target IP blocks. As a result, the platform is capable of testing multiple blocks concurrently. Once a test has been completed, tester pins may be immediately reconfigured and assembled into new port configurations to conduct a completely different set of tests.
The architecture of Tester 100 provides support for concurrent tests on potentially dozens of ports with different sequencing and digital data rates. The test-processor-per-pin architecture of Tester 100 allows it to function as a scalable platform. Tester 100 supports test technologies that include RF, analog, digital and mixed signal, each fully capable of being used concurrently. FIG. 2 illustrates the placing of DUT 160 on packaged parts DUT board 150, and the positioning of DUT board 150 above test head 110.
FIG. 3 illustrates a wafer prober DUT board 155 on top of DUT interface 120. Several further components are then stacked atop wafer prober DUT board 155; pogo tower 165; probe card 180 and wafer to be tested 190. DUT board 155, stiffener assembly 170 and pogo tower 165, together form a Wafer Prober Interface (WPI), which is made in two sizes: a 9.5 inch WPI and a 12 inch WPI. A WPI DUT board (small or large, corresponding to 512 or 1024 pins) connects the pogo pins of the test head electronics to the pogo pins of pogo tower 165. It also maps the rectangular pogo pin layout of the test head to the circular contact layout of the pogo tower probe card. A standard DUT board provided by Agilent contains an EEPROM that identifies the board. Customized WPI DUT boards may have different pin mapping, connect several pins, or provide relays and filter circuits.
FIG. 6 shows a DUT load board 200 with 16 device locations 210. System-on-a-chip ICs that are to be tested on Tester 100 are loaded one-by-one onto a DUT load board 200 of test head 110. Electronic tests are then performed on each of the SOC ICs, after the completion of which the SOC ICs are removed one-by-one from DUT load board 200, which is plugged into test head 110.
FIG. 4 shows a conceptual time line for an existing DUT board 200 approach to testing. Specifically, time to load (300, 310) devices or DUTs onto DUT load board 200 test locations 210 and time to unload (320, 330) devices or DUTs from DUT load board 200 test locations 210, no electronic testing of devices occurs. As can be seen in the time line 350, the time it takes to unload a group of devices that have been tested and then load a second group of devices to be tested onto a test head 110 is dead time, in which no testing is occurring. This dead time for device or DUT loading (300, 310) and unloading (320, 330) is referred to as the index time. The testing time is shown conceptually as 340 and 345 on the testing time line 350. Currently, the index time for most SOC IC testers is up to approximately 10% of test time.
As IC testing is expensive and time consuming, it will be readily appreciated that reducing the index time, and thus the overall test time, will be advantageous. Reducing the amount of time consumed loading and unloading DUTs onto test heads will result in a reduction in the time and correspondingly, the cost required to test ICs.